`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/28 01:51:45
// Design Name: 
// Module Name: test_image
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
 
 
module test_image;
 
reg i_clk;
reg [7:0] Bmp_tmps [0:100000];
reg [7:0] Images;
 
integer fids,idx=0,dat;
integer Rw,Ch;
//E:\A_FPGA_proj\count3\project_1\project_1.srcs\sources_1 路徑改為自己的路徑 
 
initial 
begin
fids = $fopen("E:\\A_FPGA_proj\\count3\\project_1\\project_1.srcs\\sources_1\\lena2.bmp","rb");
dat  = $fread(Bmp_tmps,fids);
Rw = {Bmp_tmps[21],Bmp_tmps[20],Bmp_tmps[19],Bmp_tmps[18]};
Ch = {Bmp_tmps[25],Bmp_tmps[24],Bmp_tmps[23],Bmp_tmps[22]};
$fclose(fids);
end
 
initial 
begin
i_clk=1;
end 
 
always #5  i_clk=~i_clk;
 
always@(posedge i_clk) 
begin
Images<=Bmp_tmps[idx];
idx<=idx+1;
end
 
 
 
endmodule

仿真結果如下：